Version: 9.16.0
WhileLoop.cxx
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1// Copyright (C) 2006-2026 CEA, EDF
2//
3// This library is free software; you can redistribute it and/or
4// modify it under the terms of the GNU Lesser General Public
5// License as published by the Free Software Foundation; either
6// version 2.1 of the License, or (at your option) any later version.
7//
8// This library is distributed in the hope that it will be useful,
9// but WITHOUT ANY WARRANTY; without even the implied warranty of
10// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11// Lesser General Public License for more details.
12//
13// You should have received a copy of the GNU Lesser General Public
14// License along with this library; if not, write to the Free Software
15// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16//
17// See http://www.salome-platform.org/ or email : webmaster.salome@opencascade.com
18//
19
20#include "WhileLoop.hxx"
21#include "Runtime.hxx"
22#include "OutputPort.hxx"
23#include "Visitor.hxx"
24#include <iostream>
25
26//#define _DEVDEBUG_
27#include "YacsTrace.hxx"
28
29using namespace YACS::ENGINE;
30using namespace std;
31
32const char WhileLoop::NAME_OF_INPUT_CONDITION[]="condition";
33
34WhileLoop::WhileLoop(const std::string& name):Loop(name),_conditionPort(NAME_OF_INPUT_CONDITION,this)
35{
36}
37
38WhileLoop::WhileLoop(const WhileLoop& other, ComposedNode *father, bool editionOnly):Loop(other,father,editionOnly),
39 _conditionPort(other._conditionPort,this)
40{
41 //Copy Data linking
42 std::vector< std::pair<OutPort *, InPort *> > linksToReproduce=other.getSetOfInternalLinks();
43 std::vector< std::pair<OutPort *, InPort *> >::iterator iter=linksToReproduce.begin();
44 for(;iter!=linksToReproduce.end();++iter)
45 {
46 OutPort* pout = iter->first;
47 InPort* pin = iter->second;
48 edAddLink(getOutPort(other.getPortName(pout)),getInPort(other.getPortName(pin)));
49 }
50}
51
52void WhileLoop::init(bool start)
53{
54 Loop::init(start);
56}
57
59{
61 return;
62 if(_inGate.exIsReady())
63 {
68 {
70 _nodeForNullTurnOfLoops=new FakeNodeForLoop(this,false,true);
71 }
72 else
74 {
75 bool normalFinish=getAllOutPortsLeavingCurrentScope().empty();
77 _nodeForNullTurnOfLoops=new FakeNodeForLoop(this,normalFinish);
78 }
79 else
80 {
83 }
84 }
85}
86
87Node *WhileLoop::simpleClone(ComposedNode *father, bool editionOnly) const
88{
89 return new WhileLoop(*this,father,editionOnly);
90}
91
92InputPort *WhileLoop::getInputPort(const std::string& name) const
93{
95 return (InputPort*)&_conditionPort;
96 return Loop::getInputPort(name);
97}
98
100
107{
108 _nbOfTurns++;
110 {
112 return YACS::FINISH;
113 }
114 else
115 {
116 node->init(false);
117 node->exUpdateState();
118 }
119 return YACS::NOEVENT;
120}
121
123 const std::list<ComposedNode *>& pointsOfViewStart,
124 InPort *end,
125 const std::list<ComposedNode *>& pointsOfViewEnd)
126{
127 DEBTRACE("WhileLoop::checkLinkPossibility");
128}
129
131{
132 visitor->visitWhileLoop(this);
133}
134
135std::list<InputPort *> WhileLoop::getLocalInputPorts() const
136{
137 list<InputPort *> ret;
138 ret.push_back((InputPort *)&_conditionPort);
139 return ret;
140}
#define DEBTRACE(msg)
Definition: YacsTrace.hxx:31
Base class for all composed nodes.
OutPort * getOutPort(const std::string &name) const
std::vector< std::pair< OutPort *, InPort * > > getSetOfInternalLinks() const
InputPort * getInputPort(const std::string &name) const
Get an input port given its name.
std::set< OutPort * > getAllOutPortsLeavingCurrentScope() const
List all output ports of children nodes that are linked to out of scope input ports.
std::string getPortName(const PORT *port) const
bool edAddLink(OutPort *start, InPort *end)
Add a dataflow link between two data ports.
bool exIsReady() const
Definition: InGate.cxx:126
Base class for Input Ports.
Definition: InputPort.hxx:44
virtual void exInit(bool start)
Definition: InputPort.cxx:63
virtual bool isEmpty()
Definition: InputPort.cxx:70
Base class for loop node.
Definition: Loop.hxx:147
void init(bool start=true)
Definition: Loop.cxx:319
friend class FakeNodeForLoop
Definition: Loop.hxx:149
FakeNodeForLoop * _nodeForNullTurnOfLoops
Definition: Loop.hxx:154
Base class for all nodes.
Definition: Node.hxx:70
InGate _inGate
Definition: Node.hxx:86
virtual void exUpdateState()
Update the node state.
Definition: Node.cxx:206
virtual void init(bool start=true)
Definition: Node.cxx:102
void setState(YACS::StatesForNode theState)
Sets the given state for node.
Definition: Node.cxx:652
InPort * getInPort(const std::string &name) const
Definition: Node.cxx:239
YACS::StatesForNode _state
Definition: Node.hxx:91
virtual void visitWhileLoop(WhileLoop *node)=0
Class for a while loop.
Definition: WhileLoop.hxx:39
static const char NAME_OF_INPUT_CONDITION[]
Definition: WhileLoop.hxx:41
ConditionInputPort _conditionPort
Definition: WhileLoop.hxx:42
Node * simpleClone(ComposedNode *father, bool editionOnly=true) const
Definition: WhileLoop.cxx:87
void checkLinkPossibility(OutPort *start, const std::list< ComposedNode * > &pointsOfViewStart, InPort *end, const std::list< ComposedNode * > &pointsOfViewEnd)
Definition: WhileLoop.cxx:122
void exUpdateState()
Update the node state.
Definition: WhileLoop.cxx:58
void init(bool start=true)
Definition: WhileLoop.cxx:52
virtual void accept(Visitor *visitor)
Definition: WhileLoop.cxx:130
YACS::Event updateStateOnFinishedEventFrom(Node *node)
Method used to notify the node that a child node has ended.
Definition: WhileLoop.cxx:106
InputPort * getInputPort(const std::string &name) const
Get an input port given its name.
Definition: WhileLoop.cxx:92
std::list< InputPort * > getLocalInputPorts() const
redefined on derived class of ComposedNode. by default a ComposedNode has no port by itself
Definition: WhileLoop.cxx:135
WhileLoop(const WhileLoop &other, ComposedNode *father, bool editionOnly)
Definition: WhileLoop.cxx:38
Event
Definition: define.hxx:56
@ NOEVENT
Definition: define.hxx:57
@ FINISH
Definition: define.hxx:59
@ ACTIVATED
Definition: define.hxx:41
@ DONE
Definition: define.hxx:43
@ DISABLED
Definition: define.hxx:50