Version: 9.16.0
Switch.hxx
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1// Copyright (C) 2006-2026 CEA, EDF
2//
3// This library is free software; you can redistribute it and/or
4// modify it under the terms of the GNU Lesser General Public
5// License as published by the Free Software Foundation; either
6// version 2.1 of the License, or (at your option) any later version.
7//
8// This library is distributed in the hope that it will be useful,
9// but WITHOUT ANY WARRANTY; without even the implied warranty of
10// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11// Lesser General Public License for more details.
12//
13// You should have received a copy of the GNU Lesser General Public
14// License along with this library; if not, write to the Free Software
15// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16//
17// See http://www.salome-platform.org/ or email : webmaster.salome@opencascade.com
18//
19
20#ifndef __SWITCH_HXX__
21#define __SWITCH_HXX__
22
25#include "ElementaryNode.hxx"
26#include "AnyInputPort.hxx"
27#include "OutPort.hxx"
28
29#include <map>
30
31namespace YACS
32{
33 namespace ENGINE
34 {
35 class Switch;
36
38 {
39 friend class Switch;
40 private:
41 int edGetNumberOfOutLinks() const;
42 std::set<InPort *> edSetInPort() const;
43 bool isAlreadyLinkedWith(InPort *withp) const;
44 std::string getNameOfTypeOfCurrentInstance() const;
45 void edRemoveAllLinksLinkedWithMe() ;
46 TypeOfChannel getTypeOfChannel() const;
47 void getAllRepresented(std::set<OutPort *>& represented) const;
48 bool addInPort(InPort *inPort) ;
49 int removeInPort(InPort *inPort, bool forward) ;
50 public:
51 void getHumanReprOfIncompleteCases(std::ostream& stream) const;
52 private://Specific part
53 bool removePotentialProducerForMaster();
54 void checkConsistency(LinkInfo& info) const;
55 CollectorSwOutPort(Switch *master, InPort *port);
56 CollectorSwOutPort(const CollectorSwOutPort& other, Switch *master);
57 void addPotentialProducerForMaster(OutPort *port);
58 bool checkManagementOfPort(OutPort *port) ;
59 private:
61 std::string _className;
63 std::map<int, OutPort *> _potentialProducers;
64 };
65
67 {
68 friend class Switch;
69 private:
73 private:
74 FakeNodeForSwitch(Switch *sw, bool normalFinish, bool internalError=false);
76 Node *simpleClone(ComposedNode *father, bool editionOnly) const;
77 void exForwardFailed();
78 void exForwardFinished();
79 void execute();
80 void aborted();
81 void finished();
82 };
83
85 {
86 friend class FakeNodeForSwitch;
87 friend class CollectorSwOutPort;
88 public:
89 static const char DEFAULT_NODE_NAME[];
90 static const char SELECTOR_INPUTPORT_NAME[];
91 static const int ID_FOR_DEFAULT_NODE;
92 protected:
94 std::map< int , Node * > _mapOfNode;//Nodes ownered
96 std::map<InPort *, CollectorSwOutPort * > _outPortsCollector;
97 mutable std::vector<CollectorSwOutPort *> _alreadyExistingCollectors;
98 public:
99 Switch(const Switch& other, ComposedNode *father, bool editionOnly);
100 Switch(const std::string& name);
101 ~Switch();
102 void exUpdateState();
103 void init(bool start=true);
104 //Node* DISOWNnode is a SWIG notation to indicate that the ownership of the node is transfered to C++
105 Node *edSetDefaultNode(Node *DISOWNnode);
106 Node *edReleaseDefaultNode() ;
107 Node *edReleaseCase(int caseId) ;
108 Node *edGetNode(int caseId);
109 Node *edSetNode(int caseId, Node *DISOWNnode) ;
110 void edChangeCase(int oldCase, int newCase);
111 virtual bool edAddChild(Node *DISOWNnode) ;
112 int getMaxCase();
113 void getReadyTasks(std::vector<Task *>& tasks);
114 std::list<Node *> edGetDirectDescendants() const;
115 InputPort *edGetConditionPort() { return &_condition; }
116 void writeDot(std::ostream &os) const;
117 int getNumberOfInputPorts() const;
118 int getMaxLevelOfParallelism() const;
119 void getWeightRegardingDPL(ComplexWeight *weight);
120 void partitionRegardingDPL(const PartDefinition *pd, std::map<ComposedNode *, YACS::BASES::AutoRefCnt<PartDefinition> >& zeMap);
121 void edRemoveChild(Node *node) ;
122 std::list<InputPort *> getSetOfInputPort() const;
123 std::list<InputPort *> getLocalInputPorts() const;
124 YACS::StatesForNode getEffectiveState() const;
125 YACS::StatesForNode getEffectiveState(const Node* node) const;
126 OutPort *getOutPort(const std::string& name) const ;
127 InputPort* getInputPort(const std::string& name) const ;
128 Node *getChildByShortName(const std::string& name) const ;
129 std::string getMyQualifiedName(const Node *directSon) const;
130 std::string getCaseId(const Node *node) const ;
131 virtual void accept(Visitor *visitor);
132 int getRankOfNode(Node *node) const;
133 virtual std::string typeName() {return "YACS__ENGINE__Switch";}
134 std::list<ProgressWeight> getProgressWeight() const;
135 protected:
136 YACS::Event updateStateOnFinishedEventFrom(Node *node);
137 Node *simpleClone(ComposedNode *father, bool editionOnly=true) const;
138 std::set<InPort *> getAllInPortsComingFromOutsideOfCurrentScope() const;
139 void checkLinkPossibility(OutPort *start, const std::list<ComposedNode *>& pointsOfViewStart,
140 InPort *end, const std::list<ComposedNode *>& pointsOfViewEnd) ;
141 void buildDelegateOf(std::pair<OutPort *, OutPort *>& port, InPort *finalTarget, const std::list<ComposedNode *>& pointsOfView);
142 void getDelegateOf(std::pair<OutPort *, OutPort *>& port, InPort *finalTarget, const std::list<ComposedNode *>& pointsOfView) ;
143 void releaseDelegateOf(OutPort *portDwn, OutPort *portUp, InPort *finalTarget, const std::list<ComposedNode *>& pointsOfView) ;
144 void checkCFLinks(const std::list<OutPort *>& starts, InputPort *end, unsigned char& alreadyFed, bool direction, LinkInfo& info) const;
145 void checkControlDependancy(OutPort *start, InPort *end, bool cross,
146 std::map < ComposedNode *, std::list < OutPort * > >& fw,
147 std::vector<OutPort *>& fwCross,
148 std::map< ComposedNode *, std::list < OutPort *> >& bw,
149 LinkInfo& info) const;
150 void checkNoCyclePassingThrough(Node *node) ;
151 private:
152 int getNbOfCases() const;
153 static std::string getRepresentationOfCase(int i);
154 };
155 }
156}
157
158#endif
#define YACSLIBENGINE_EXPORT
std::map< int, OutPort * > _potentialProducers
Definition: Switch.hxx:63
Base class for all composed nodes.
Base class for all calculation nodes.
Node * simpleClone(ComposedNode *father, bool editionOnly) const
Definition: Switch.cxx:245
FakeNodeForSwitch(Switch *sw, bool normalFinish, bool internalError=false)
Definition: Switch.cxx:230
Base class for Input Ports.
Definition: InputPort.hxx:44
Class that deal with list of semantics links for high level analysis.
Definition: LinkInfo.hxx:83
Base class for all nodes.
Definition: Node.hxx:70
Control node that emulates the C switch.
Definition: Switch.hxx:85
InputPort * edGetConditionPort()
Definition: Switch.hxx:115
std::vector< CollectorSwOutPort * > _alreadyExistingCollectors
Definition: Switch.hxx:97
static const int ID_FOR_DEFAULT_NODE
Definition: Switch.hxx:91
std::map< int, Node * > _mapOfNode
Definition: Switch.hxx:94
virtual std::string typeName()
Definition: Switch.hxx:133
std::map< InPort *, CollectorSwOutPort * > _outPortsCollector
Definition: Switch.hxx:96
AnyInputPort _condition
Definition: Switch.hxx:93
FakeNodeForSwitch * _undispatchableNotificationNode
Definition: Switch.hxx:95
Event
Definition: define.hxx:56
StatesForNode
Definition: define.hxx:34